{
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  "slug": "bqp-physical-bounding-universal-quantum-computation-under-correlated-noise-and-c",
  "title": "BQP_physical: Bounding Universal Quantum Computation under Correlated Noise and Causality Constraints",
  "authors": [
    "Rowan Brad Quni-Gudzinas"
  ],
  "abstract": "Universal gate‑based quantum computers promise exponential speed‑ups for problems such as integer factorisation, yet commercial‑scale devices remain absent. The gap originates from physical limits that are not captured by the abstract class BQP. We formalise a new class BQP_physical that incorporates three concrete constraints: (i) finite signal‑propagation latency across macroscopic processor dimensions, (ii) a correlated‑error floor that grows with qubit count, and (iii) a coherence‑time budget consumed by quantum error correction. Using a processor dimension of 10 m, a per‑gate error target of 10^-3, a correlated‑error coefficient of 10^-5 per qubit pair, and a typical superconducting gate duration of 20 ns, we derive (a) a total propagation latency of 33~mus for a depth‑10³ circuit, (b) a maximal viable qubit count of approximately 10 when the logical error budget is relaxed to 10^-2, and (c) a logical error probability exceeding 1 for a Shor‑scale processor with N=10⁴ qubits. These quantitative results imply that, without radical architectural changes, Shor‑scale factoring lies outside BQP_physical. The framework therefore redirects design effort toward architectures that suppress correlated noise and latency, and provides a concrete analytical benchmark for future experimental validation.",
  "abstract_markdown": "Universal gate‑based quantum computers promise exponential speed‑ups for problems such as integer factorisation, yet commercial‑scale devices remain absent. The gap originates from physical limits that are not captured by the abstract class BQP. We formalise a new class **BQP_physical** that incorporates three concrete constraints: (i) finite signal‑propagation latency across macroscopic processor dimensions, (ii) a correlated‑error floor that grows with qubit count, and (iii) a coherence‑time budget consumed by quantum error correction. Using a processor dimension of 10 m, a per‑gate error target of \\(10^{-3}\\), a correlated‑error coefficient of \\(10^{-5}\\) per qubit pair, and a typical superconducting gate duration of 20 ns, we derive (a) a total propagation latency of \\(33~\\mu\\text{s}\\) for a depth‑\\(10^{3}\\) circuit, (b) a maximal viable qubit count of approximately 10 when the logical error budget is relaxed to \\(10^{-2}\\), and (c) a logical error probability exceeding 1 for a Shor‑scale processor with \\(N=10^{4}\\) qubits. These quantitative results imply that, without radical architectural changes, Shor‑scale factoring lies outside **BQP_physical**. The framework therefore redirects design effort toward architectures that suppress correlated noise and latency, and provides a concrete analytical benchmark for future experimental validation.",
  "date": "2026-10-26",
  "first_published": "2026-10-26",
  "last_revised": "2026-10-26T00:00:00Z",
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  "url": "https://papers.qnfo.org/papers/bqp-physical-bounding-universal-quantum-computation-under-correlated-noise-and-c",
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  "sha256": "5e25b01aaaff7df24bf66912154056ea7ce9d6c0f5046e793f1d45863c4ad0fe",
  "version_url": "https://papers.qnfo.org/papers/bqp-physical-bounding-universal-quantum-computation-under-correlated-noise-and-c/v/1.0.0",
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    "titles": [
      {
        "title": "BQP_physical: Bounding Universal Quantum Computation under Correlated Noise and Causality Constraints"
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    "publicationYear": "2026",
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        "description": "Universal gate‑based quantum computers promise exponential speed‑ups for problems such as integer factorisation, yet commercial‑scale devices remain absent. The gap originates from physical limits that are not captured by the abstract class BQP. We formalise a new class BQP_physical that incorporates three concrete constraints: (i) finite signal‑propagation latency across macroscopic processor dimensions, (ii) a correlated‑error floor that grows with qubit count, and (iii) a coherence‑time budget consumed by quantum error correction. Using a processor dimension of 10 m, a per‑gate error target of 10^-3, a correlated‑error coefficient of 10^-5 per qubit pair, and a typical superconducting gate duration of 20 ns, we derive (a) a total propagation latency of 33~mus for a depth‑10³ circuit, (b) a maximal viable qubit count of approximately 10 when the logical error budget is relaxed to 10^-2, and (c) a logical error probability exceeding 1 for a Shor‑scale processor with N=10⁴ qubits. These quantitative results imply that, without radical architectural changes, Shor‑scale factoring lies outside BQP_physical. The framework therefore redirects design effort toward architectures that suppress correlated noise and latency, and provides a concrete analytical benchmark for future experimental validation.",
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