A New Way to Classify Computers by Their Physics

In the paper's words

Special-purpose accelerators, neuromorphic chips, and optical processors are today evaluated by qubit or transistor counts, yet the machines that deliver the largest effective speedups are those whose physical dynamics directly embodies the target problem. This paper addresses a specific gap: no existing framework defines when a physical system's relaxation dynamics is equivalent to a problem's solution structure, and no hardware taxonomy classifies machines by the mechanism that achieves many candidate solutions simultaneously. We formalize "Hamiltonian isomorphism" as an equivalence relation between a target problem's cost structure and a physical system's energy function, and we propose classifying computing hardware by its physical simultaneity mechanism rather than by its information unit.

The abstract, verbatim, and its opening sentence is the claim. Every line below is quoted from the text.

Numbers it reports

1. At the gate-based end, Medha [1] is a microcoded FPGA accelerator for homomorphic encryption: ten RPAU units on an Alveo U250, 200 MHz clock, on-chip memory only to avoid DDR transfer overhead, and — most instructive for us — a placement problem so severe that manual placement over months of iterations was needed because congestion can drive the clock down or make routing impossible even when individual blocks meet timing.

   from 2. Background and Related Work

2. Its resource profile (63.2% LUTs, 23.2% registers, 58.6% BRAMs, 72.7% URAMs, 29.3% DSPs) quantifies the silicon cost of a programmable arithmetic engine, which we treat as the resource density of the calculation paradigm.

   from 2. Background and Related Work

3. The resource profile of [1] (63.2% LUTs, 58.6% BRAMs, 72.7% URAMs) becomes, in our vocabulary, the measured cost of $M = 0$ simultaneity.

   from 7. Practical Implications and Engineering Pathways

4. A cloud operator outsourcing homomorphic computations today confronts software implementations so slow that dedicated programmable hardware is required to make the service usable at all; even then, the accelerator of [1] runs at 200 MHz and consumes 63.2% of the LUTs, 58.6% of the BRAMs and 72.7% of the URAMs of a Xilinx Alveo U250 card to deliver that usability.

   from 1. Introduction

5. Its resource profile — 63.2% of LUTs, 58.6% of BRAMs, 72.7% of URAMs on the Alveo U250 — is the silicon paid for sequential programmability rather than for symmetry.

   from 4.4 Mode-count accounting for the taxonomy classes

6. As a principal quantitative result, we derive that the thermodynamic floor for a gate-based logical operation under a stated error-correction overhead of $10^{2}$ to $10^{3}$ physical operations per logical operation is $2.87\times 10^{-19}$ to $2.87\times 10^{-18}$ joules at 300 K, while a relaxation machine that reaches its ground state once pays only the single-bit resetting cost of $2.87\times 10^{-21}$ joules per output read — a separation of two to three orders of magnitude that motivates the taxonomy.

   from Abstract

How it is done

1. As a principal quantitative result, we derive that the thermodynamic floor for a gate-based logical operation under a stated error-correction overhead of $10^{2}$ to $10^{3}$ physical operations per logical operation is $2.87\times 10^{-19}$ to $2.87\times 10^{-18}$ joules at 300 K, while a relaxation machine that reaches its ground state once pays only the single-bit resetting cost of $2.87\times 10^{-21}$ joules per output read — a separation of two to three orders of magnitude that motivates the taxonomy.

   from Abstract

2. We prove that Hamiltonian isomorphism is an equivalence relation, derive the structural conditions a problem class must satisfy to admit such a mapping, and show — using the known complexity of isomorphism problems for computable structures [6] — that the meta-problem of classifying which problems admit such mappings is itself severe, which bounds the ambition of any universal taxonomy.

   from 1. Introduction

3. That work computes the Landauer bound — erasing one bit dissipates at least $kT\ln 2$, approximately $2.9\times 10^{-21}$ joules at 300 K — and shows that the quantum generalization changes nothing: erasing a qubit costs the same $kT\ln 2$ per qubit because a maximally mixed qubit carries at most one bit of von Neumann entropy.

   from 2. Background and Related Work

4. Following the methodological requirement of [7] that a foundational relation be reflexive, symmetric, and transitive, we prove: Proposition 3.5.

   from 3.2 Hamiltonian isomorphism is an equivalence relation

What would falsify it

1. A falsifiable experimental program: simulate the relaxation dynamics of candidate Hamiltonians and verify solution emergence at critical points, with the specific measurement and refutation criterion stated (Section 7).

   from 1. Introduction

2. The main quantitative claim (R2) is falsified if either: (a) a fault-tolerant logical operation is demonstrated with $N_{\text{ec}} \lt 10$ physical operations per logical operation at scale, collapsing the gate-based floor toward the single-bit value; or (b) a relaxation machine is built whose per-instance dissipation, including programming and readout, measurably exceeds $(n_{\text{out}}+1)kT\ln 2$ by a factor that grows with problem size faster than $N_{\text{gates}} N_{\text{ec}}$ does — i.e., if the hidden costs scale superlinearly in instance size while gate counts scale linearly.

   from 6. Discussion

3. Observation (b) in particular would show the A1 model omits the dominant physics.

   from 6. Discussion

Where the claim stops

1. Assumption A1 treats step (ii), the relaxation itself, as quasistatic and nondissipative in the zero-noise limit.

   from 6. Discussion

2. Real substrates pay at least three costs A1 does not model: (i) the energy dissipated in the analog hardware that implements $H$ (pump lasers, resistive elements, amplifier loops), which in present devices dominates $kT\ln 2$ by many orders of magnitude; (ii) the energy to program the Hamiltonian, which for a reconfigurable substrate is a per-instance cost analogous to $N_{\text{ec}}$; and (iii) readout noise, which may force repetition, multiplying the $(n_{\text{out}}+1)kT\ln 2$ floor by an attempt count.

   from 6. Discussion

3. Condition 4 (dynamical convergence) is assumed, not characterized.

   from 6. Discussion

Where to read

1. Abstract253 words · 1 min
2. 1. Introduction668 words · 3 min
3. 2. Background and Related Work1,201 words · 5 min
4. 3. Methods962 words · 4 min
5. 4. Analysis1,109 words · 5 min
6. 5. Results316 words · 1 min
7. 6. Discussion659 words · 3 min
8. 7. Practical Implications and Engineering Pathways645 words · 3 min
9. 8. Conclusion224 words · 1 min
10. Provenance and AI Involvement225 words · 1 min