Thermodynamic Feedback Limits on the Scalability of Surface‑Code Quantum Error Correction

In plain language

The paper set out to find whether the heat generated by control electronics and wiring during each error‑correction step would warm the qubits, raise their intrinsic error rate, and create a feedback loop that blocks scaling up. It connected the logical error chance to the physical error rate, the physical error rate to temperature with an Arrhenius‑type rule, and the temperature rise to the power per qubit using a thermal resistance of 5 K W⁻¹. Plugging in typical values (power per qubit = 10⁻⁶ W, thermal resistance = 5 K W⁻¹) the model predicts a temperature increase of ΔT = 750 K for a processor with one million qubits. The logical‑error formula pL ≈ 0.1 (p/pth)^{(d+1)/2} uses a threshold pth ≈ 1.78×10⁻¹, and the analysis shows that keeping the physical error below this threshold would require the processor temperature to stay below about 1 K even when N = 10⁶. The authors note that any experiment showing a stable temperature below 1 K while scaling to N ≥ 10⁶

Restated for a non-expert reader; the original wording follows. Still uses some technical language.

In the paper's words

Quantum error correction (QEC) is essential for fault‑tolerant quantum computation, yet the control electronics, wiring, and cryogenic heat load required for each correction cycle generate heat that raises the qubit temperature and thereby increases the intrinsic physical error rate. This creates a positive feedback loop—an error‑correction chasm—that can preclude scalable fault tolerance. We couple a standard surface‑code threshold model to a thermodynamic budget by (i) expressing the logical error probability p_L as a function of the physical error probability p, (ii) relating p to the qubit temperature T through an Arrhenius‑type law, and (iii) linking T to the dissipated power per qubit via a thermal resistance and, alternatively, via a heat‑capacity model.

The abstract, verbatim; every line below is quoted from the text.

What it claims

that the feedback loop yields a temperature rise independent of system size and pushes error rates above threshold—would be falsified by any empirical observation showing a stable operating temperature at millikelvin levels while scaling N to 10⁶ qubits without a corresponding increase in error probability. Specifically, a measurement of the processor temperature after a full QEC cycle that remains within <1 K for N≥10⁶ would contradict the derived Δ T=750 K.

Numbers it reports

1. Assuming a breakthrough that reduces per‑qubit control ASIC power to $\$10$ per qubit and that the dilution refrigerator cost scales linearly with cooling power, a 1‑million‑qubit system would require roughly $ 10 M for ASICs plus $ 1 M for a refrigerator capable of 1 W cooling at 20 K.

   from (e) Projected cost/performance bounds (projection)

2. The surface‑code family, a leading candidate for fault‑tolerant architectures, exhibits a high threshold around $p_{\text{th}}\approx1.78\times10^{-1}$ under depolarising noise [3].

   from 2. Background and Related Work

3. For a surface code of distance $d$, the logical error probability per round is approximated by $$ p_{\mathrm{L}} \approx A\left(\frac{p}{p_{\mathrm{th}}}\right)^{(d+1)/2}, $$ where $p$ is the physical error probability, $p_{\mathrm{th}}=10^{-2}$ is the canonical surface‑code threshold [1], and $A\approx0.1$ is a constant fitted to Monte‑Carlo data in the literature [1].

   from 3.1 Surface‑code logical error model

4. The average power per qubit is therefore $$ P_{\mathrm{q}} = E_{\mathrm{c}}\,f = 10^{-12}\,\mathrm{J}\times10^{6}\,\mathrm{s^{-1}} = 10^{-6}\,\mathrm{W}. $$ The temperature rise above the refrigerator base temperature $T_{\mathrm{base}}$ is given by $$ \Delta T = P_{\mathrm{q}}\,R_{\mathrm{th}}, $$ where $R_{\mathrm{th}}=5\,\mathrm{K\,W^{-1}}$ is a representative thermal resistance of the wiring and chip interface [7].

   from 3.3 Thermodynamic budget – resistance model

5. Each QEC cycle dissipates a fixed amount of heat per qubit: $$ q_{\text{elec}} = 5\times10^{-13}\,\mathrm{J},\qquad q_{\text{wire}} = 1\times10^{-12}\,\mathrm{J}, $$ so that the total per‑qubit dissipation is $$ q_{\text{tot}} = q_{\text{elec}} + q_{\text{wire}} = 1.5\times10^{-12}\,\mathrm{J}. $$ For a processor with $N$ qubits, the total heat generated per cycle is $Q = N\,q_{\text{tot}}$ and the total heat capacity is $C = N\,c\,v$.

   from 3.4 Thermodynamic budget – heat‑capacity model

6. A stable operating point requires that the physical error probability after a cycle remains below the fault‑tolerance threshold $p_{\mathrm{th}}=0.178$ (toric‑code threshold reported in [3]): $$ p(T) \le p_{\mathrm{th}}. $$ Substituting the expressions for $p(T)$ and $T$ yields two inequalities, one for each thermodynamic model.

   from 3.5 Fixed‑point condition

How it is done

1. For a surface code of distance $d$, the logical error probability per round is approximated by $$ p_{\mathrm{L}} \approx A\left(\frac{p}{p_{\mathrm{th}}}\right)^{(d+1)/2}, $$ where $p$ is the physical error probability, $p_{\mathrm{th}}=10^{-2}$ is the canonical surface‑code threshold [1], and $A\approx0.1$ is a constant fitted to Monte‑Carlo data in the literature [1].

   from 3.1 Surface‑code logical error model

2. Each qubit undergoes a correction cycle of duration $t_{\mathrm{c}}=1\,\mu\mathrm{s}$ (frequency $f=1\,\mathrm{MHz}$).

   from 3.3 Thermodynamic budget – resistance model

3. Alternatively, we model the processor material with volumetric heat capacity $c=2\times10^{-3}\,\mathrm{J\,K^{-1}\,cm^{-3}}$ and qubit volume $v=10^{-12}\,\mathrm{cm^{3}}$ [4].

   from 3.4 Thermodynamic budget – heat‑capacity model

4. Although $p=0.0125$ is below this threshold, the temperature of $750\,\mathrm{K}$ is far beyond any cryogenic capability, indicating that the system cannot physically sustain the required operating point.

   from 4.2 Heat‑capacity‑model temperature rise

What would falsify it

1. The central claim—that the feedback loop yields a temperature rise independent of system size and pushes error rates above threshold—would be falsified by any empirical observation showing a stable operating temperature at millikelvin levels while scaling $N$ to $10^{6}$ qubits without a corresponding increase in error probability.

   from 7.2 Failure modes and falsifiability

2. Observation of a temperature rise that drives $p$ above the threshold at the predicted $P_{\mathrm{q}}^{\max}$ would falsify the model.

   from (c) Minimal de‑risking experiment

Where the claim stops

1. Assumption Description Sensitivity Linear thermal resistance $R_{\mathrm{th}}=5\,\mathrm{K\,W^{-1}}$ Assumes constant resistance across the relevant power range.

   from 7.1 Limitations

2. No additional cooling beyond the refrigerator Assumes all heat must be removed by the base stage.

   from 7.1 Limitations

3. If any of these assumptions are substantially violated—e.g., if per‑qubit dissipation can be reduced by two orders of magnitude—the temperature rise would drop to $\sim7.5\,\mathrm{K}$, still far above the millikelvin regime but potentially manageable with advanced cryogenics.

   from 7.1 Limitations

Where to read

1. Abstract216 words · 1 min
2. 1. Introduction286 words · 1 min
3. 2. Background and Related Work135 words · 1 min
4. 3. Methods306 words · 1 min
5. 4. Analysis451 words · 2 min
6. 5. Results201 words · 1 min
7. 6. Extended Derivations and Worked Examples872 words · 4 min
8. 7. Discussion309 words · 1 min
9. 8. Practical Implications and Engineering Pathways357 words · 2 min
10. 9. Conclusion120 words · 1 min
11. Provenance and AI Involvement225 words · 1 min